Revealing the Hysteresis-Free Electrical Property of Tellurium p-FET through Pulse and Low-Temperature Measurement

Sung-Tsun Wang^1,2*, Kai-Wei Li¹, Chun-Hung Lin¹, Der-Hsien Lien¹

¹Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
²Institute of Pioneer Semiconductor Innovation, National Yang Ming Chiao Tung University, Hsinchu, Taiwan

* Presenter:Sung-Tsun Wang, email:beckham880415@gmail.com

Tellurium (Te) is one of the strong p-type channel candidates for future 3D integrated circuits. Although Te Field Effect Transistors (FETs) exhibit superior electrical properties, the Te FETs suffer from a significant hysteresis issue during stair signal measurement. The mechanism of hysteresis can be speculated that its origin lies in interface traps and traps induced by physisorbed gas. In this study, pulse measurement and low-temperature measurement are applied to eliminate the hysteresis caused by trapping. Unlike sampling measurements, pulse measurement provides a recovery period between each measurement point, during which no bias is applied to the FET. This allows the FET to recover from the previous biasing, reducing the trapping influence on subsequent measures. On the other hand, low-temperature measurement can prevent the trapping process from occurring, as the process is unable to obtain sufficient activation energy under low temperatures. Both strategies achieved a small hysteresis measurement result, in which the current under different gate voltages is closer to the intrinsic, unbiased condition. As a result, the hysteresis of Te FET was reduced by approximately 80 %. Additionally, the On/Off ratio of the Te FET can reach 3~4 orders of magnitude, and its mobility can reach up to 50 cm² V^-1s^-1, demonstrating excellent potential as an ideal p-type channel material.

Keywords: Tellurium, Hysteresis, Interface trap, Low-temperature measurements, Pulse measurements