Monolithic 3D integration of vertically stacked CFET devices and circuits with high-mobility In2O3 n-FET and tellurium p-FET
Tzu-Ting Weng1*, Der-Hsien Lien1, Yu-Lun Chueh2
1Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
2Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu, Taiwan
* Presenter:Tzu-Ting Weng, email:teresaweng1751@gmail.com
Complementary field-effect transistors—which have n-type and p-type field-effect transistors (FETs) vertically stacked on top of each other—can boost area efficiency in integrated circuits. Here we report heterogeneous complementary FETs that combine p-type tellurium (Te) thin film transistor (TFT) and n-type In2O3 TFT. A low temperature is employed to fabricate the Te and In₂O₃ channel materials, which is compatible with M3D technology in the back-end of line (BEOL) temperature limitation. The In2O3 NMOS and Te PMOS device show an on/off current ratio exceeding 107 and 104 respectively, and the integrated M3D inverters indicate an average voltage gain of ≈ 13.8 V/V at VDD = 3 V. A static random-access memory (SRAM) with high reliability which is composed of two integrated M3D inverters is also demonstrated. The noise margin can be up to 80% of supply voltage and perform the symmetrical window. The vertically-stacked complementary field-effect transistors (CFET) with high energy-efficiency can increase the circuit density in a chip to conform the development of next-generation semiconductor technology.


Keywords: Integrated circuits, monolithic 3D integration, oxide semiconductor, tellurium